1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including transistor elements comprising gate structures on the basis of a high-k gate dielectric material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, the scaling of the channel length, and associated therewith the reduction of channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows performing subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of the thin gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. The relatively high leakage current, however, caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide based gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with thermal design power requirements for many types of circuits.
Therefore, replacing silicon dioxide based dielectrics as the material for gate insulation layers has been considered, particularly for devices requiring extremely thin silicon dioxide based gate dielectric layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer results in a capacitive coupling that would otherwise only be obtained by an extremely thin silicon dioxide layer.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since the threshold voltage of the transistors, which represents the voltage at which a conductive channel forms in the channel region, is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
Providing different metal species for adjusting the work function of the gate electrode structures for P-channel transistors and N-channel transistors at an early manufacturing stage may, however, be associated with a plurality of difficulties, which may stem from the fact that a complex patterning sequence may be required during the formation of the sophisticated high-k metal gate stack, which may result in a significant variability of the resulting work function and thus threshold of the completed transistor structures.
For this reason, in other approaches, the initial gate electrode stack may be provided with a high degree of compatibility with conventional polysilicon-based process strategies and the actual electrode metal and the final adjustment of the work function of the transistors may be accomplished in a very advanced manufacturing stage, i.e., after completing the basic transistor structure.
A corresponding manufacturing strategy is also referred to as a replacement gate approach or technology in which at least the adjustment of the work function, i.e., the incorporation of appropriate work function metal species, is accomplished in a very late manufacturing stage. Furthermore, in some cases, the high-k dielectric material may be formed upon patterning the gate electrode structure, thereby avoiding the deposition of the high-k dielectric material, possibly in combination with an additional very thin silicon oxide material in a very late manufacturing stage. In other cases, a so-called full replacement approach may be applied by forming the high-k dielectric material in a late manufacturing stage together with the work function metal species and the actual electrode metal. Generally, the replacement gate strategy is a very promising technology, wherein, however, upon further scaling the transistor dimensions and thus the gate length, increasingly, deposition-related irregularities are caused upon filling in the actual electrode metal, as will be explained in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 in a final stage of a replacement gate approach. As shown, the device 100 comprises a substrate 101, such as a semiconductor material or any other appropriate carrier material for forming thereon a semiconductor layer 102, such as a silicon layer, a silicon/germanium layer and the like. The semiconductor layer 102 is typically divided into a plurality of semiconductor regions or active regions on the basis of appropriate isolation structures (not shown) in order to define the lateral size and positions for forming transistor elements. For example, in FIG. 1, a first active region 102A, which may correspond to an N-channel transistor 150A and a second active region 102B corresponding to a P-channel transistor 150B are depicted. In this manufacturing stage, the transistors 150A, 150B comprise drain and source regions 151 and a channel region 152 having appropriate dopant profiles so as to correspond to the characteristics of the transistors 150A, 150B. Furthermore, a contact level 120 is provided in an intermediate manufacturing stage and may comprise appropriate dielectric materials, such as a dielectric layer 121 and a dielectric layer 122, which are typically provided in the form of silicon nitride and silicon dioxide, respectively. The dielectric materials 122, 121 laterally enclose gate electrode structures 160A, 160B of the transistors 150A, 150B, respectively. As discussed above, initially the gate electrode structures 160A, 160B may be provided in the form of well-established polysilicon/silicon dioxide gate electrode structures, wherein at least the polysilicon material has been removed and is thus replaced by an appropriate material system. For example, a first layer 161A is illustrated and is to represent at least a metal-containing electrode material, while in some cases the layer 161A may also represent a high-k dielectric material, possibly in combination with an oxide layer 166, while in other cases, as discussed above, the layer 166 may represent a high-k dielectric material provided in an early manufacturing stage, possibly in combination with an additional conventional dielectric material (not shown). The layer 161A typically comprises an appropriate work function metal species, such as lanthanum and the like, possibly in combination with titanium nitride, wherein at least one conductive barrier or etch stop layer, such as tantalum nitride, is provided so as to protect and passivate any underlying materials. Furthermore, the layer 161A is also provided in the gate electrode structure 160B in combination with a second metal-containing electrode material 161B, which may be provided in the form of titanium nitride and which may provide a desired work function of the gate electrode structure 150B in combination with the previously provided material layer 161A. Moreover, in the manufacturing stage shown, an electrode metal 162, such as aluminum and the like, is formed in the gate electrode structures 160A, 160B, which, however, may result in deposition-related irregularities, such as a void 162V, in particular in the gate electrode structure 160B which has a reduced width for filling in the electrode metal 162 due to the presence of the layer 161B.
The semiconductor device 100 as illustrated in FIG. 1 may be formed on the basis of the following process strategy. In an early phase, the active regions 102A, 102B are formed by incorporating appropriate dopant species for defining the basic characteristics of the transistors 150A, 150B, while the lateral position, size and shape of the active regions 102A, 102B is determined by providing an appropriate isolation structure, such as a shallow trench isolation. To this end, well-established manufacturing techniques, including implantation processes and masking regimes for incorporating an appropriate well dopant species may be applied, while isolation structures may be formed by using sophisticated lithography, etch, deposition, anneal and planarization techniques. Thereafter, the gate electrode structures 160A, 160B are formed in an initial and thus preliminary state by, for instance, forming an appropriate silicon dioxide-based dielectric material followed by polysilicon material and any additional sacrificial materials, such as hard mask materials and the like, as required for patterning the gate electrode structures 160A, 160B in compliance with the overall design rules of the device 100. For example, in sophisticated applications, a gate length of 40 nm and less has to be implemented, wherein sophisticated transistors may even require a gate length of 30 nm and less in the device 100. Thereafter, the processing is continued by, for instance, forming a spacer structure 163 and also providing the drain and source regions 151 using well-established process techniques, such as implantation processes, selective epitaxial growth techniques and the like. If required, anneal processes are applied in order to activate dopant species and re-crystallize implantation-induced damage. Next, the contact level 120 is formed by depositing the materials 121, 122, for instance by applying chemical vapor deposition (CVD) techniques, spin-on techniques and the like, possibly in combination with planarization processes in order to provide a planar surface. Thereafter, any excess material is removed so as to finally expose a surface of the placeholder material, i.e., of the polysilicon material, which is then removed by using highly selective etch recipes, thereby forming respective openings in the gate electrode structures 160A, 160B. Thereafter, the layer 161A is deposited, for instance, by using very conformal CVD-like deposition techniques, such as atomic layer deposition (ALD), which may include the deposition of a high-k dielectric material, as discussed above, while in other cases a corresponding high-k dielectric material may have been formed in an early manufacturing stage. The deposition of the layer 161A comprises the deposition of at least one metal-containing electrode material, such as tantalum nitride, that is formed in a highly conformal manner so as to act as an etch stop material without unduly deteriorating the overall electronic characteristics and conductivity of the gate electrode structures 160A, 160B. As discussed above, when realizing a gate length of 40 nm and significantly less, the material layer 161A, possibly including the high-k dielectric material, has to be deposited into a high aspect ratio opening obtained by the removal of the placeholder material. Typically, the layer 161A is formed with a thickness of several nm when comprising a high-k dielectric material and an appropriate work function adjusting material layer. Consequently, upon forming the layer 161B, for instance in the form of a titanium nitride material, which may have to be provided with a significantly increased thickness of up to 5 nm and more, in order to obtain the required electronic characteristics of the gate electrode structure 160B, even more sophisticated deposition conditions are encountered during the deposition of the layer 161B. To this end, also highly conformal deposition recipes are applied, for instance on the basis of ALD and the like. Next, typically, appropriate lithography techniques and etch strategies are applied so as to selectively remove the layer 161B from the gate electrode structure 160A. Thereafter, the processing is continued by depositing the electrode metal 162, for instance in the form of aluminum. Due to the previous deposition of the layer 161B, however, the resulting width of the gate opening is significantly reduced, for instance by approximately 10 nm for a layer thickness of 5 nm, thereby significantly increasing the probability of creating voids 162V in the gate electrode structure 160B, which in turn has a pronounced impact on the overall characteristics of the transistor 150B, which may even result in a total failure of the transistor 150B. In order to attempt to completely fill the gate electrode structures 160A, 160B, it has been suggested to use a CVD deposition for aluminum which, however, may require, due to the self-limiting nature of the CVD-aluminum deposition processes, an additional titanium seed layer, which may cause a non-desired overhang at the top of the gate structures, thereby even further reducing the available gap, in particular in the gate electrode structure 160B upon depositing the actual electrode metal 162.
Since it is extremely difficult to completely fill the gate electrode structures having an aspect ratio, i.e., a ratio of length of the corresponding gate openings with respect to the depth thereof, of up to 10, other strategies have been proposed in order to reduce the sophisticated aspect ratio. For example, in some conventional approaches, it has been proposed to reduce the aspect ratio by increasing the width of the gate openings, for instance upon or after removing the placeholder material by using appropriate material erosion processes, such as plasma assisted etch processes, ion sputtering techniques and the like. In this manner, a substantially tapered cross-sectional shape of the corresponding gate openings, as indicated by 168, may be obtained, thereby significantly reducing the complexity of the subsequent deposition processes. In this manner, even the initially high aspect ratio openings may be reliably filled with the electrode metal 162. Since the tapered portion 168 may, however, result in a significantly increased gate length at the upper portions of the gate electrode structures 150A, 150B, in particular in densely packed device areas, the increased gate length may be in conflict with a contact regime in which contact elements are to be formed in the contact level 120 adjacent to the gate electrode structures 160A, 160B so as to connect to the drain and/or source regions 151. In this case, an increased pitch between closely spaced gate electrode structures has to be implemented, thereby significantly increasing the overall lateral size of complex semiconductor devices.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.